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Postdoctoral Scholar Research Associate - Reconfigurable Computi
ARLINGTON VA 22204
Category: Education
  • Your pay will be discussed at your interview

Job code: lhw-e0-90671785

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University of Southern California

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  Job posted:   Thu Jun 7, 2018
  Distance to work:   ? miles
       
  2 Views, 0 Applications  
 
Postdoctoral Scholar Research Associate - Reconfigurable Computi
Postdoctoral Scholar Research Associate - Reconfigurable ComputingApplyInformation Sciences InstituteArlington, Virginia



Information Sciences Institute (ISI), a unit of USC's Viterbi School of Engineering, is a world leader in the research and development of advanced information processing, computing, and communications technologies. ISI operates one of the world's largest academic high-performance computing clusters. ISI has three research campuses: one in Marina Del Rey, CA; one in Arlington, VA; and one in Waltham, MA.



*This position is located in Arlington, VA.*



The Reconfigurable Computing Group at the University of Southern California's Information Sciences Institute is a long-time pioneer of research investigating Field Programmable Gate Arrays. Spanning the days of homogeneous logic devices to today's billion transistor System on Chip devices, RCG has led the way from being the first to implement application level partial runtime reconfiguration, investigating 3D FPGA architectures, developing Autonomous System on Chip architectures, releasing open source CAD tools which target real physical devices, IP to address software / hardware co-design complexity and continues today with research ranging from developing programming models for next generation industry devices to conducting experiments on the International Space Station. Today, RCG is addressing our nation's challenges in big data, hardware cybersecurity, trusted systems, cognitive radio and more.



USC/ISI is looking for highly talented, motivated researchers to lead and impact state of the art research and development in the area of reconfigurable computing. This position will lead research in algorithm development for custom internal tools which target FPGA and ASIC front end design. These tools solve challenging problems in hardware security, high level abstraction for hardware design, and machine learning acceleration for critical systems. Realize effectiveness of solutions on physical FPGAs and custom ASIC fabrication. Lead research, propose major innovations, collaborate with peers within the group and across ISI, publish results in top tier conferences, and contribute to or lead proposals.



Fixed term position: 1 yr with 1 yr renewals



Required Qualifications



+ Applicants selected for this position will require access to ITAR materials. According to U.S. government regulations, ONLY U.S. citizens OR lawful permanent residents (green card) are eligible for ITAR access.




+ PhD in Computer Engineering, Electrical Engineering, or Computer Science required.


+ Experience with Machine Learning and/or Graph partitioning algorithms targeting FPGAs or ASICs.


+ Experience designing, developing, implementing, and debugging firmware for FPGAs, including Xilinx Virtex7 or later architectures. Experience with Intel Aria-10 and Stratix-10 devices also desirable.


+ C++/Java and Python development experience, including contributions to large-scale software projects, commercial or open-source.


+ Solid understanding of CAD algorithms including synthesis, partitioning, mapping, placing, and routing.


+ Expert level use of Xilinx or Intel FPGA implementation tools, including High level synthesis.


+ Previous publications, patents, or innovations related to FPGA productivity, CAD or EDA algorithms and tools.




Preferred Qualifications:



+ Detailed understanding of mapped and unmapped netlist formats, such as EDIF, XDL, and structural Verilog.


+ Proficiency in software cross-compiling and cross-debugging


+ Experience with Torc, ABC, VPR, VTR, RapidSmith, GoAhead, or similar tools a plus.


+ Experience with Amazon EC2 F1 instances or related FPGA-based cloud platforms.


+ Experience with multi-processor system-on-chip, embedded systems software (Linux, cross-compilers) and Python productivity for FPGAs (i.e. Pynq).


+ Experience with multi-processor system-on-chip, embedded systems software (Linux, cross-compilers) and Python productivity for FPGAs (i.e. Pynq).


+ Experience leading or contributing to proposals a significant plus.




The University of Southern California values diversity and is committed to equal opportunity in employment.




REQ20060544 Posted Date: 06/05/2018

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